This relates to a power distribution network for an integrated circuit package.
A typical integrated circuit package includes an array of connectors on an exterior surface of the package. FIG. 1 depicts an illustrative example of a portion of one such array 100 of connectors 110 on a package substrate 130. Connectors 110 are solder balls or solder bumps and will be referred to collectively hereafter as “pins.” The pins are organized in groups 120 that are referred to as “banks.” Within each bank 120 in a typical package, there is one power supply pin 112 for every eight to twelve input/output (I/O) signal pins 114. Thus, for a typical bank of 40 to 50 pins, there are three to five power supply pins distributed among the pins of the bank. The number of pins and the number of banks varies widely with the type of integrated circuit package. For some packages, the number of pins is well in excess of 1000.
Array 100 is formed on the exterior surface of package substrate 130. Substrate 130 is a multi-layer structure comprising a series of electrically conducting metal layers that are insulated from one another by intermetallic dielectric layers. Each of the layers is substantially parallel to the exterior surface of the package. Interconnection paths are defined in the metal layers; and selective connections are made by vias between the paths in the various layers so as to connect the pins of array 100 to bonding pads (not shown) on the interior surface of substrate 130 opposite the exterior surface. At least one of the metal layers is used to interconnect the power supply pins 112. Further details on package substrates are found in R. R. Tummala (Ed.), Fundamentals of Microsystems Packaging (McGraw-Hill 2001), which is incorporated herein by reference.
As a result of these arrangements, a substantial number of the available pins are used for power supply, thereby reducing the number of pins available for use as input/output signal pins or requiring the use of a larger substrate to accommodate more I/O pins. Further, distributing the power supply pins complicates the layout of the pins and imposes constraints that are likely to make the final arrangement of pins less than optimal. The need to connect the power supply pins with a metal layer embedded in the substrate further complicates the design of the package substrate and may increase the layer count.
The performance of a typical circuit with a relatively large number of power supply pins is also less than desired. Within the frequency range of operation for these circuits, which is approximately 1 MHz to approximately 1 GHz, the system level impedance of these circuits varies substantially and has two peaks. Moreover, the lower frequency impedance peak exceeds the desired impedance by a factor of about 2.